Device for in-service monitoring of communication transmission equipment

ABSTRACT

In a device for error locating and/or in-service monitoring for communication transmission equipment comprising a call unit (7, 8) that exchanges information with processor units (6) and wherein the processor units (6) are provided with addresses, a data bus (9, 9A...9H) that connects the telemetry channels of a plurality of transmission links (4; 4a...4g; 4AB...4EG) to one another is provided at at least one location (A...H).

BACKGROUND OF THE INVENTION

The invention is directed to a device for inservice monitoring ofcommunication transmission equipment that contain at least onetransmission link having two line terminal equipment between which oneor more intermediate locations may be provided. Also provided is amonitoring unit that exchanges information via at least one telemetrychannel with processor units that are allocated to monitored local endsand/or intermediate locations.

Such a device is already known from Ewald Braun and Erhard Steiner,"Supervision and Additional Services for Digital Fiber-OpticTransmission Systems" telcom report 10 (1987) Special "Multiplexing andLine Transmission", pages 107 through 112.

In the known device for in-service monitoring of a communicationtransmission equipment, useful signals are transmitted via anelectrooptical transmission link and telemetry signals are transmittedvia an auxiliary channel. The device uses address-free telemetrytelegrams, so that the processor units provided in the line terminalequipment and intermediate repeaters of a transmission link need not beaddressed. The method, however, cannot be employed without further adoin communication transmission equipment that have a star or,respectively, tree structure.

SUMMARY OF THE INVENTION

It is therefore an object of the invention to create a device thatallows branched communication transmission equipment to be monitored.

A structure that corresponds to the useful signal network therebyderives for the telegram transmission network of the telemetry means.Processor units that are polled by the monitoring unit in cyclicalsuccession under address control can thus be provided in the telegramtransmission network of the appertaining telemetry means in acommunication transmission network having star or, respectively, treestructure.

The device for achieving this object has the following elements: theprocessor units are provided with addresses; and the monitoring unitcomprises a means for transmitting polling telegrams that containaddresses to the processor units and comprises a means for receiving areply telegram of the processor unit that is respectively called; andthe communication transmission equipment contains a plurality ofprocessor units at at least one location, these being connected to oneanother via a data bus that connects the telemetry channels of aplurality of transmission links to one another.

What derives in communication transmission equipment that form acommunication transmission network composed of line sections and whereinthe line sections each respectively comprise a telemetry channel on thebasis of these measures is the advantage that a telemetry network havingthe desired configuration can be created with the assistance ofidentical devices.

Advantageous developments of the invention are as follows. The data busconnecting the processor units can be a bidirectional bus forhalf-duplex operation. The processor unit contains at least oneinput/output for the connection of a four-wire telemetry channel andcontains at least one input/output for the connection of the data busand contains a switching equipment that, upon receipt of data at theinput of one of the input/outputs in a quiescent condition, forwards andreceived data to the outputs of the other inputs/outputs.

An OR element or an exclusive-OR element precedes the output at each ofthe inputs/outputs of the processor unit and two inputs of the ORelement or, respectively, exclusive-OR element are connected to theinputs of the two other inputs/outputs.

The output at each of the inputs/outputs of the processor unit isconnected to a data output of a microprocessor and upon reception ofdata at the input of one of the inputs/outputs, the microprocessorforwards the received data to the outputs of the other inputs/outputs.

The output at each of the inputs/outputs of the processor unit isconnected to a data output of the microprocessor and given reception ofdata on at least two inputs of the inputs/outputs, the microprocessordies not forward the received data to the outputs of the otherinputs/outputs.

A switch-over means precedes each of the outputs at the processor unit,the switch-over means optionally connecting the switching equipment or adata output of the microprocessor to the appertaining output.

At least those processor units connected to the data bus eachrespectively contain a transmission-reception unit and thetransmission-reception units are controllable by a microprocessor of therespective processor unit such that, in the quiescent condition, alltransmitters of the transmission-reception units are high-impedance attheir output and output a prescribed logic level when transmitting data.

The transmission-reception unit is controllable by a means for signaledge recognition such that a timer element is started by the signal edgeof a start bit of data incoming at one of the telemetry inputs, thetimer element activating the transmitter of the transmission-receptionunit for the duration of at least two characters and simultaneouslyinhibiting a receiver of the transmission-reception unit. A furtherholding and disconnect is assumed by the microprocessor to which thedata are simultaneously supplied.

The inputs/outputs can be four-wire terminals or two-wire terminals. Inparticular, a four-wire terminal is respectively provided for thetelemetry signal channel and a four-wire and/or a two-wire terminal isprovided for the data bus.

The microprocessor can transmit monitoring data of the appertainingoperating location or can optionally transmit data in a protected modeor in a store-and-forward mode, whereby the data transmission ensues viathe appertaining switch-over means instead of ensuing via the OR or,respectively, exclusive-OR elements.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention shall be set forth in greater detail with reference toexemplary embodiments shown in the figures.

The figures show devices for in-service monitoring of communicationtransmission equipment, namely

FIG. 1 having a fundamental digital signal line section;

FIG. 2 having a line network composed of three fundamental digitalsignal line sections;

FIG. 3 having a star network containing a plurality of parallel lines;

FIG. 4 having a branched star network;

FIG. 5 a processor unit.

DESCRIPTION OF THE PREFERRED EMBODIMENT

Line terminal equipment, intermediate repeaters and light waveguides arethe basic elements of the digital signal transmission link shown in FIG.1 whose functionability and transmission properties are monitored withthe assistance of devices of a means for in-service monitoring that iscomposed of the locating module 7, of the personal computer 8 and of thein-service monitoring processor units referred to below as processorunits 6.

The locating module can be eliminated when the processor units 6 areexecuted such that they can be connected either as a master or as aslave. One processor unit 6 must then be connected as master and mustassume the jobs of the locating module, and the remaining processorunits must be connected as slaves.

The smallest unit of a digital signal transmission link is a fundamentaldigital signal line section 4, referred to as line section 4 below. Inthe transmission equipment of FIG. 1, the line section is composed oftwo line terminal equipment 1 and of one or more intermediate repeaters2 inserted into the link as needed.

A processor unit 6 that receives monitoring data from the main system tobe monitored via an internal bus is inserted into every line terminalequipment 1 and into every intermediate repeater 2.

Dependent on the demands, the locating domain can be composed of thefollowing structures:

a line that, according to FIG. 2, is composed of one or more linesections 4 connected in cascade;

according to FIG. 3, a network having parallel lines;

according to FIG. 4, a star network provided with branchings.

Every processor unit 6 is controlled by a microprocessor and isconstructed in conformity with FIG. 5. It has a terminal K2 in the lineterminal equipment 1 and has two terminals K1 and K2--respectively onefor each of the two directions--in the intermediate repeater 2 forinfeed and outfeed into and out of the auxiliary channel superimposed onthe useful signal. A terminal K3 or, respectively, K3a for a networknode is additionally provided.

Dependent upon the application, the terminal K3a having twounidirectional interfaces or the terminal K3 having a bidirectionalinterface is employed.

The data of the processor units 6 are coupled out within a line section4 via the terminals K1, K2 and are transmitted in the auxiliary channelthat is preferably superimposed on the useful signal.

Within a line, the data of the processor units 6 are transmitted fromline terminal equipment 1 to line terminal equipment 1 via the four-wireterminals K1, K2, are coupled into and out of the auxiliary channel and,as warranted, are transmitted from one line section 4a to the next linesection 4b via the terminals K3 or, respectively, K3a.

In the arrangement shown in FIG. 2, the line sections 4a...4c areconnected in a chain. The locating module is connected to the processorunit 6 of the line terminal equipment 1 in one of the two local ends ofthe chain circuit. A personal computer 8 is connected to this locatingmodule 7. Further personal computers 8 are connected directly to theprocessor unit 6 of the first line terminal equipment 1 and to two ofthe intermediate repeaters 2n.

Useful signals are transmitted from line terminal equipment 1 to lineterminal equipment 1 within the line sections 4a...4c. The data of theprocessor units 6 are transmitted within the line sections 4a...4c via arespective auxiliary channel and are 15 transmitted between the linesections 4a...4c via a respective ISM bus (in-service-monitoring bus) 9having the interface RS 485 (terminal K3 of the processor unit 6).

In addition, all processor units 6 have a terminal 90, particularlyhaving the interface RS 232 C, to which a personal computer 8 can beconnected. This possibility is utilized at one line terminal equipmentand at two intermediate repeaters.

FIG. 3 shows two of a plurality of lines that end at the network node N(branch).

The processor units of the line terminal equipment 1 and the locatingmodule 7 are connected to one another at the network node N via the ISMbus 9.

According to FIG. 4, the locations A through G are connected to oneanother via a branched star network. A line section 4AB withoutintermediate repeater is provided between the locations A and B; twoline sections 4BC1, 4BC2 each having an intermediate repeater 2 areprovided between the locations B and C; a line section 4BD is providedbetween the location B and the location D and a respective line section4 DF and 4GE is provided between the location D and F and D and G. Thelocation E is also connected to the intermediate repeater 2 of the linesection 4BC2 via a line section 4E.

A respective personal computer 8 is connected to the processor unit ofthe line terminal equipment 1 at the locations A and C. The personalcomputer 8 can thereby optionally be connected at the ISM bus 9 with theinterface RS 485 or at an additional terminal of the processor unithaving the interface RS 232 C. In addition to the line terminalequipment 1 of the line sections ending there, the locating module 7 isconnected to the ISM bus 9 at the location D, this locating module 7being provided with a means for polling control. In addition, thelocating module 7 has a terminal 70 for connection of a signalcollecting means via which the monitoring data of the star network canbe polled by the locating module 7 on the basis of the signal collectingmeans.

At a branch, the data of the processor unit 6 are transmitted betweenthe line terminal equipment 1 via the terminals K3 or, respectively, K4and via the network node.

In the networks of FIGS. 1 through 4, an equipment for executivesequencing, particularly a locating module 7 and/or a personal computer8, is connected to one of the network nodes or to one of the processorunits. The locating module 7 or a personal computer 8 successively pollsthe individual processor units 6 via a call-in telegram with theiraddresses, receives their monitoring data per reply telegram andevaluates these monitoring data.

As may be seen from the figures, a locating domain can be composed of aplurality of fundamental digital signal line sections. The terminal K3of the processor unit is provided for forwarding the inservicemonitoring data from one fundamental digital signal line section to thenext fundamental digital signal line section of a line network or tofurther fundamental digital signal line sections connected to a networknode.

This terminal can be composed of two unidirectional interfaces, of adata input and of a data output. In this case, the data of all outputsare expediently conducted into all inputs at the branch locations viaintrinsically known four-wire terminations. On the other hand, aconnector as disclosed by German Patent 20 48 140 can, for example, beemployed for this purpose.

The distribution of the data in the network nodes can be undertaken withlower outlay via a bidirectional bus. In order to avoid data collisions,however, only respectively one driver dare be active at a bus. Givenemployment of a bidirectional bus, the following sequence is thereforeprovided for the activation and connection of a bus driver:

All drivers are inactive in the quiescent condition and have ahigh-impedance output. When data arrive at a terminal K1, K2, a timerthat activates the driver for at least two characters is started by thesignal edge of the start bit. The continued holding and disconnect isthen assumed by the microcomputer to which the data are supplied inparallel. Switching into a mode wherein all data are checked beforebeing passed on and wherein only correct data are forwarded is carriedout only when a disturbance in the transmission occurs--recognized byparity or check sum infringement or infringement of a cyclic redundantcode (cyclic redundancy check) or non-coincidence of a length byte. Thismode can be activated and deactivated by the locating module via aremote control instruction.

The advantage of this method is that the data are quicklythrough-connected given undisturbed transmission, so that a short querycycle derives and a locating of the error is possible given disturbedtransmission in the auxiliary channel.

The processor unit shown in FIG. 5 has an input E1 and output A1 for theconnection of a first four-wire data channel for the transmission oftelegrams, has an input E2 and output A2 for the connection of a secondfour-wire data channel and has a third input E3 and output A3 for theconnection of a third four-wire data channel.

Via a switch-over means 36, 31 or, respectively, 13 controllable by themicroprocessor 35, each of the three outputs A1, A2 and A3 can beoptionally connected to the output of an exclusive-OR element 37, 30 or,respectively, 12 or to the output of a parallel-to-serial converter 23.This parallel-to-serial converter 23 has its parallel input connected tothe port PO of the microprocessor 35. The switch-over means 36 isthereby controlled via the two-lead control line St5, the switch-overmeans 13 is controlled via the two-lead control line St3, and theswitch-over means 31 is controlled via the two-lead control line St6,being all controlled by the microprocessor 35.

The exclusive OR elements 12, 30 and 37 that each respectively lead toan output of one of the three four-wire terminals and that may bepotentially replaced by OR elements operate the data incoming at theinputs of the two other four-wire terminals.

The serial-to-parallel converters 20, 22, 24 and 25 as well as theparallel-to-serial converters 21 and 23 are contained in UART modules orin HDLC modules. The serial-to-parallel or, respectively,parallel-to-serial converters 20 through 25 are connected to the port POof the microprocessor 35 via an 8-bit parallel bus and are selected bythe ,chip select module 26 that is connected to the microprocessor 35.As needed, they interrupt the program of the microprocessor on the basisof the interrupt module 27 that is likewise connected to themicroprocessor 35.

The coding switch 29 with whose assistance the processor unit can be setto an address and to the function of an addressing line terminalequipment is also connected to the port PO of the microprocessor 35 viathe switch 28.

The RAM 32 serving as data store, the EPROM 33 serving as programmemory, the EEPROM 34 serving as non-volatile data memory and the module38 for self-monitoring are also connected to the microprocessor 35.

The output of the exclusive-OR element 12 is conducted to the one inputof the OR element 15 via the means 14a for signal edge recognition andvia the means 14b connected in chain therewith. Together with a controlinput of the means 14a and 14b, the other input of the OR element 15 isconnected to the control line St2 coming from the microprocessor 35.

The transmission-reception module 11 lies between the four-wire terminalpair E3, A3 and the bus terminal K3 for the connection of abidirectional bus. The control input of this transmission and receptionmodule 11 via which the transmitter D or the receiver R can beoptionally activated is connected to the output of the OR element 15.

During normal operation, the telegrams are forwarded from the data inputE1 or E3 via the exclusive-OR element 30 and the switch 31 directly tothe output A2. From the input E2 or E3, the telegrams proceed via theexclusive-OR element 37 and the switch 36 to the output A1.

The exclusive-OR element 12 or, respectively, 30 or, respectively, 37sees to it that no data are transmitted when data arrives simultaneouslyat the inputs E1 and E2 or, respectively, E1 and E3 or, respectively, E2and E3.

Since no data dare arrive simultaneously at the input E1, E2 and E3given error-free operation, the exclusive-OR elements 12, 37 and 30inhibit data only in the case of error.

Data that arrive at the input E1 or E2 can also proceed via theexclusive-OR element 12 and via the switch 13 to the transmitter D ofthe transmission-reception module 11 and can proceed from the latter tothe bus terminal K3. To this end, the switch 13 must be situated in theillustrated normal position and the transmitter D must be activated.This is the case when the means 14a recognizes a leading edge and the ORelement 15 receives a corresponding control potential via the means 14band/or via the control line St2.

When, during normal operation, data are conducted via the exclusive-ORelement 12 to the bus terminal K3, then these data are also suppliedinto the means 14a for signal edge recognition. When the means 14a forsignal edge recognition recognizes the leading edge of the first bit ofa telegram, then it starts the timer circuit 14b. This timer circuitoutputs an output pulse that is independent of the bit sequence thatarrives at the input of the means 14a for signal edge recognition. Theoutput pulse proceeds via the OR element 15 to thetransmission-reception module 11 and immediately activates the drivermodule D and deactivates the reception module R. Data that arrive at oneof the inputs E1 or E2 of the processor unit are thus immediatelyforwarded to the bus terminal K3 due to the recognition of a leadingedge.

The data are simultaneously transmitted to the microprocessor 35 forprocessing. Data that arrive at the input E1 proceed via theserial-to-parallel converter 22 to the microprocessor 35; data from theinput E2 proceed to the microprocessor 35 via the serial-to-parallelconverter 25; and data from the input E3 proceed to the microprocessor35 via the serial-to-parallel converter 24. The serial-to-parallelconverters 22, 24 and 25 accept the data byte-by-byte and always outputan interrupt pulse to the microprocessor 35 when they have loaded a bytein order to output it to the port PO of the microprocessor 35. When themicroprocessor 35 finds that the data satisfy prescribed demands, itactivates the control line St2. As a result thereof, the microprocessor35 activates the driver module D of the interface module 11 via the ORelement 15.

When, during the evaluation of a telegram, the microprocessor 35 findsthat given demands are not met, then it initiates the processor unit toswitch into a store-and-forward mode. In the store-and-forward mode, themicroprocessor 35 activates two of the three control lines St3, St5 andSt6. Two of the three switches 13, 31, and 36 therefore switch, so thatall data that the parallel-to-serial converter 23 outputs proceed to twoof the three outputs A1, A2, K3 from whose direction the telegram wasnot received.

The data incoming at the input E1 are processed in theserial-to-parallel converter 21; the data incoming at the input E2 areprocessed in the serial-to-parallel converter 25. The microprocessor 35thus recognizes the direction from which the data come. Instore-and-forward mode, the control lines St6 and the control lines St5are therefore activated such that the output A1 or A2 via whichtransmission is not carried out is placed at high potential via theswitch 31 or 36 and the pull-up resistor.

The signal collector 18 is connected to the microprocessor 35 via theinterface module 19 and the serial-to-parallel converter 20 and theparallel-to-serial converter 21. The signal collector 18 supplies themonitoring data of the monitored intermediate location and may receivethe control information contained in the call-in telegram for forwardingto a signal collecting means (not shown). The monitoring data of themonitored intermediate location are transmitted in all three directionsK1, K2 and K3 by the processor 35 via the parallel-to-serial converter22, via the switch-over means 13, 31, 36 and via the outputs A1, A2, A3.When, at a network node, a plurality of terminals K3 are connected toone another via a bidirectional bus, then the following sequence derivesfor the activation and deactivation of a bus driver:

All drivers are inactive in the quiescent condition and have ahigh-impedance output. When data arrive at the terminal K1 or K2, thetimer element 14b is started by the signal edge of the start bit, thistimer element 14b activating the driver for at least two characters. Thefurther holding and deactivation is then assumed by the microcomputer 35to which the data are supplied in parallel.

The invention is not limited to the particular details of the apparatusdepicted and other modifications and applications are contemplated.Certain other changes may be made in the above described apparatuswithout departing from the true spirit and scope of the invention hereininvolved. It is intended, therefore, that the subject matter in theabove depiction shall be interpreted as illustrative and not in alimiting sense.

I claim:
 1. Device for error locating and/or in-service monitoring forcommunication transmission network that contain at least onetransmission link having first and second line terminal equipmentbetween which one or more intermediate locations may be provided, havinga monitoring unit that exchanges information via at least one telemetrychannel with processor units that are allocated to monitored local endsand/or intermediate locations, the processor units having addresses, andthe monitoring unit having a means for transmitting polling telegramsthat contain addresses to the processor units and having a means forreceiving a reply telegram from a processor unit that has beenrespectively called, comprising: at at least one location in thecommunication transmission network a plurality of processor unitsconnected to one another via a data bus that connects the telemetrychannels of a plurality of transmission links to one another, eachprocessor unit of the plurality of processor units being allocated to alocal end of a respective transmission link of the plurality oftransmission links.
 2. Device according to claim 1, wherein the data busconnecting the processor units is a bidirectional bus for half-duplexoperation.
 3. Device according to claim 1, wherein at least eachprocessor unit of the plurality of processor units contains at least twoinput/output channel ports for the connection of a four-wire telemetrychannel and contains at least one input/output node port for theconnection of the data bus and contains a switching equipment that, uponreceipt of data at an input of one of the at least two input/outputchannel ports and input/output node port a quiescent condition, forwardsthe received data to outputs of the others of the at least twoinput/output channel ports and at least one input/output node port. 4.Device according to claim 3, wherein one of an OR element or anexclusive-OR element precedes the output at each of the at least twoinput/output channel ports and at least one input/output node port ofthe processor unit; and wherein two inputs of the OR element or,respectively, exclusive-OR element are connected to the inputs of thetwo other of the at least two input/output channel ports and at leastone input/output node port.
 5. Device according to claim 3, wherein theoutput at each of the at least two input/output channel ports and atleast one input/output node port of each processor unit of the pluralityof processor units is connected to a data output of a microprocessor;and wherein, upon reception of data at the input of one of the at leasttwo input/output channel ports and at least one input/output node port,the microprocessor forwards the received data to the outputs of theother of the at least two input/output channel ports and at least oneinput/output node port.
 6. Device according to claim 3, wherein theoutput at each of the of each processor unit of the plurality ofprocessor units is connected to a data output of a microprocessor; andwherein, given reception of data at at least two inputs of the at leasttwo input/output channel ports and at least one input/output node port,the microprocessor does not forward the received data to the outputs ofthe other of the at least two input/output channel ports and at leastone input/output node port.
 7. Device according to claim 3, wherein aswitch-over means precedes each of the outputs of each processor unit,said switch-over means optionally connecting the switching equipment ora data output of a microprocessor to the appertaining output.
 8. Deviceaccording to claim 1, wherein at least those processor units connectedto the data bus each respectively contain a transmission-reception unit;and wherein the transmission-reception units are controllable by amicroprocessor of the respective processor unit such that, in thequiescent condition, all transmitters of the transmission-receptionunits have a high-impedance at their output and output a prescribedlogic level when transmitting data, receivers of thetransmission-reception units being inhibited when the transmitters aretransmitting data.
 9. Device according to claim 8, wherein thetransmission-reception unit is controllable by a mans for signal edgerecognition such that a timer element is started by the signal edge of astart bit of data incoming at one of the inputs of the at least twoinput/output channel ports, said timer element activating a transmitterof the transmission-reception unit for the duration of at least twocharacters of the data and simultaneously inhibiting a receiver of thetransmission-reception unit; and wherein further control of thetransmitter and receiver is assumed by the microprocessor to which thedata are simultaneously supplied.